1. Field of Invention
The present invention relates to a structure and method of fabricating a semiconductor device. More particularly, the present invention relates to a structure and method of fabricating a flash memory cell.
2. Description of Related Art
A typical flash memory cell includes a stacked structure of a control gate and a floating gate, and a source/drain region on two sides of the structure, where the control gate and the floating gate are generally constructed of polysilicon. In a conventional method of process of a flash memory cell, a positive high voltage is applied, in a programming mode, to a control gate to cause electrons injecting to a floating gate so that the channel under the floating gate is turned off in a reading operation; while a negative high voltage is applied, in an erasing mode, to the control gate to cause electrons ejecting from the floating gate so that the channel under the floating gate is turned on in a reading operation. Data in the memory cell are judged by whether the channel is turned on.
However, over-erase often occurs in a process to erase a flash memory cell. In other words, too much electrons eject from the floating gate to cause the floating gate carrying positive charges, and thus the channel under the floating gate will have electron leakage; when the over-erase becomes more significant, the channel may even stay in an on-state to seriously interfere reading operation of other memory cells. To solve such problems, prior art provides a split-gate design, i.e., by constructing a select gate beside the floating gate and separating the select gate from a substrate with a gate oxidation layer, under which another channel for the memory cell is formed. Thus, when the channel under the floating gate continues to be turned on due to over-erase, the select gate beside the floating gate will have a function to turn on or off the channel of the memory cell. The select gate is mostly constructed of polysilicon and is patterned simultaneously with the control gate.
Even though the split-gate design in prior art may effectively avoid problems caused by over-erase, the split gate fabricating process requires two deposition steps to deposit polysilicon and thus is time consuming since the select gate is formed after the formation of the floating gate.